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CPLD Registers
7
6
5
4
3
2
1
0
R
HRRQ3
HRRQ2
HRRQ1
HRRQ0
HTRQ3
HTRQ2
HTRQ1
HTRQ0
W
Reset:
—
—
—
—
—
—
—
—
Figure 7-13. HREQ Status Register (HSR)
Table 7-10. HSR Bit Descriptions
Bits
7–4
3–0
Name
HRRQ[3–0]
HTRQ[3–0]
Description
HRRQ status from DSP[3–0]. Indicates the state of the 0
HRRQ signal from each of the MSC711x devices.
1
HTRQ status from DSP[3–0]. Indicates the state of the 0
HTRQ signal from each of the MSC711x devices.
1
Settings
HRRQ is logic low.
HRRQ is logic high.
HTRQ is logic low.
HTRQ is logic high.
7
6
5
4
3
2
1
0
R
HRRE3
HRRE2
HRRE1
HRRE0
HTRE3
HTRE2
HTRE1
HTRE0
W
Reset:
0
0
0
0
0
0
0
0
Figure 7-14. HREQ Enable Register (HER)
Table 7-11. HER Bit Descriptions
Bits
Name
Description
Settings
7–4
HRRE[3–0]
DSP[3–0] HRRQ enable. Determines whether an
HRRQ signal from an MSC711x device is used to
0
1
HRRQ is not enabled.
HRRQ is enabled.
signal the global active low HRRQ signal to the host.
3–0
HTRE[3–0]
DSP[3–0] HTRQ enable. Determines whether an
HTRQ signal from an MSC711x device is used to
0
1
HTRQ is not enabled.
HTRQ is enabled.
signal the global active low HTRQ signal to the host.
Note: The CPLD firmware is written to enable/disable the HRRQ and HTRQ signals properly when they are configured as
active low out of the MSC711x devices. If only one device is enabled at a time, the signal polarity does not matter.
MSC711x Packet Telephony Farm Card (SPT711xPFCE), Rev. 1
Freescale Semiconductor
27
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